Nowadays, many smart cards according to the standard ISO/IEC 14443A are used. These smart cards are also used in conjunction with SIM modules. In standard applications the smart cards are directly connected with an antenna via analog signal lines. However, for other applications of smart cards, particularly when they are employed in SIM modules, it would also be desirous to directly connect existing types of smart cards with near field communication (NFC) devices without the need to provide separate antennas for both the smart card and the NFC device. In order to connect smart cards and NFC devices with each other; it is necessary to connect said devices via a protocol converter rather than connecting them directly, since the signal protocols and interfaces of smart cards and NFC devices are not compatible with each other. Specifically, the digital interfaces (S2C interface) of NFC devices cannot be connected to the antenna lines of smart cards, since these lines are analog signal lines. The problems associated with the present inefficient solutions for matching NFC devices and smart cards will be explained now in greater detail with reference to the block diagram of FIG. 1.
FIG. 1 shows a block circuit diagram of a configuration of an NFC device 1 indirectly connected to a smart card 2 which both per se are compliant with the international standard ISO 14443A. In order to enable communication between the NFC device 1 and the smart card 2, a protocol converter 7 is switched between the NFC device 1 and the smart card 2. It should be noted that in this configuration only the NFC device 1 is connected to an antenna 3 at its input. The protocol converter 7 converts the signals flow between a digital interface of the NFC device 1 comprising the digital output line SIGOUT and the digital input line SIGIN and an analog interface of the smart card 2 comprising the bidirectional analog lines La and Lb. All mentioned devices are connected to ground potential GND. The NFC device 1 receives electromagnetic signals ES from the antenna 3 and comprises a demodulator 4 being adapted to demodulate the electromagnetic signals ES and to convert them into square-wave signals DES (see FIG. 5) that are transmitted via line SIGOUT. The NFC device 1 further comprises a load modulator 5 being adapted to modulate the electromagnetic signals ES transmitted from a card reader/writer (not shown). The protocol converter 7 converts the digital square-wave signals DES received via line SIGOUT into analog signals and transmits said analog signals via lines La, Lb to the smart card 2. The smart card 2 processes the received analog signals by extracting information and instructions from them and, if necessary, sends an analog response signal R1 via lines La, Lb which is converted by the protocol converter 7 into a digital response R2 that controls the load modulator 5 of the NFC device 1. The drawback of this known system, however, is that the timing of the resulting response RS from the NFC device 1 to the RFID reader/writer does not any longer comply with ISO 14443, but due to the signal delays mainly caused by the signal conversion within the protocol converter 7, are outside of the specifications of ISO 14443, as will now be explained with reference to the timing diagram of FIG. 5.
The uppermost line in the timing diagram of FIG. 5 depicts the electromagnetic signal ES that is transmitted by the RFID reader/writer as is received at the antenna 3. The electromagnetic signal ES comprises a carrier signal CS that has been ASK modulated with a serial data signal DS. The data signal DS is compliant with the Modified Miller Code which defines the value ‘0’ or ‘1’ of a bit by the position of a predefined signal pattern PA, i.e. a short pause in the signal flow. If the pause occurs at the half-bit period the value of the bit is ‘1’. If there is no pause within the bit length or the pause is considerably offset from the half-bit period, the value of the bit is ‘0’. The timings of the pauses are precisely defined in ISO 14443 and are shown in the timing diagram of FIG. 3.
It is apparent from FIG. 3 that the electromagnetic signal ES that has been ASK modulated with the data signal DS comprises a predefined signal pattern PA that is represented by a signal pause. The pause within the data signal DS is initiated by a falling signal edge as a first characteristic component FE and ends with a rising signal edge as a second characteristic component RE. When the length of the initiating falling edge is taken into account a length t1 of the pause may vary between 2 μs and 3 μs. When the length t3 of the rising edge is also taken into account the length (t1+t3) of the pause may be up to 4.5 μs. The absolute minimum value t2 of the pause, which is reached when no edges are taken into account, is 0.5 μs. It should be noted that due to physical conditions an RFID reader/writer operating in an RF field tends to produce signals having relatively long edges. It should further be observed that the specifications of ISO 14443 allow for some tolerances in the design of RFID communication systems.
In FIG. 5, second line it is shown that the demodulator 4 within the NFC device 1 has converted the analog electromagnetic signal ES into a digital square-wave signal DES having a frequency that is equal to the frequency of the carrier signal CS, i.e. 13.56 MHz for RFID communication systems according to IS 14443. Due to the digital nature of the square-wave signal DES, the lengths of the rising and falling edges are negligible in respect to the overall length t1 of the pause.
It should also be noted that according to ISO 14443 data between the RFID reader/writer on the one hand and the NFC device on the other hand are exchanged by way of frames, i.e. series of data bits and optional error detection bits, with frame delimiters at start and end. Further, there is a so called frame delay time FDT which is defined as the time between two frames transmitted in opposite directions. The frame delay time FDT must not remain under a defined minimum frame delay time and must not exceed a defined maximum frame delay time either. For communication in direction from the RFID reader/writer, the frame delay time FDT is defined as the time between the end (rising edge RE) of the last pause PA transmitted by the RFID reader/writer and the first modulation edge ME within the startbit of the response signal RS transmitted by the NFC device 1. The frame delay time FDT is defined as an integer multiple of the carrier signal frequency and typically amounts to 91 μs. The above described timings can be best seen in the timing diagram of FIG. 4. However, as has already been explained above, with the known RFID communication system of FIG. 1 this timing specification cannot be fulfilled due to internal signal delays t5 that are mainly caused by the protocol converter 7. For a better illustration of these timing problems it is once more referred to the timing diagram of FIG. 5. The third line of this diagram shows a correct response signal RS of a standard-conform stand-alone NFC device which response signal RS is delayed by the frame delay time FDT that is triggered by the end (rising edge RE) of the last pause PA transmitted by the RFID reader/writer. On the other hand, the fourth line of this diagram shows a response signal RS produced by the RFID communication system according to FIG. 1. It is apparent that the response signal RS is not only delayed by the frame delay time FDT, but is also delayed by the internal delay time t5. The sum of the frame delay time FDT and the internal delay time t5 exceeds the admissible response delay time so that the known RFID communication system operates outside of the specifications of ISO 14443.